-------------------------------------------------------------------------------
-- 
-- Sesion 4 lunes dia 13 de diciembre de 2010
-- Added:
--        architecture BlockRAM
-------------------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;

entity reg_file is
  generic(
    W : NATURAL := 8;
    B : NATURAL := 10
  );
  port(
    clk, reset: in std_logic;
    wr_en: in std_logic;
    w_addr, r_addr: in std_logic_vector (B-1 downto 0);
    w_data: in std_logic_vector (W-1 downto 0);
    r_data: out std_logic_vector (W-1 downto 0)
  );
end reg_file;

--architecture arch of reg_file is
--  type reg_file_type is array (2**B-1 downto 0) of std_logic_vector(W-1 downto 0);
--  signal array_reg: reg_file_type;
--begin
--  process (clk, reset)
--  begin
--    if (reset='1') then
--      array_reg <= (others=>(others=>'0'));
--    elsif (clk'event and clk='1') then
--      if wr_en='1' then
--        array_reg(to_integer(unsigned(w_addr))) <= w_data;
--      end if;
--    end if;
--  end process;
--
--  -- read port output multiplexer
--  r_data <= array_reg(to_integer(unsigned(r_addr)));
--
--end arch;

architecture DistRAM of reg_file is
  type reg_file_type is array (2**B-1 downto 0) of std_logic_vector(W-1 downto 0);
  signal array_reg: reg_file_type;
begin
  process (clk)
  begin
--    if (reset='1') then
--      array_reg <= (others=>(others=>'0'));
--    else
    if (clk'event and clk='1') then
      if wr_en='1' then
        array_reg(to_integer(unsigned(w_addr))) <= w_data;
      end if;
    end if;
  end process;

  -- asynchronous read port
  r_data <= array_reg(to_integer(unsigned(r_addr)));

end DistRAM;

--architecture BlockRAM of reg_file is
--  type reg_file_type is array (2**B-1 downto 0) of std_logic_vector(W-1 downto 0);
--  signal array_reg: reg_file_type;
--begin
--  process (clk)
--  begin
----    if (reset='1') then
----      array_reg <= (others=>(others=>'0'));
----    else
--    if (clk'event and clk='1') then
--      if wr_en='1' then
--        array_reg(to_integer(unsigned(w_addr))) <= w_data;
--      end if;
--      -- synchronous read port
--      r_data <= array_reg(to_integer(unsigned(r_addr)));
--    end if;
--  end process;
--
--end BlockRAM;
